Solid-state storage is memory which uses electronic circuitry, typically in integrated circuits, for storing data rather than conventional magnetic or optical media like disks and tapes. Solid-state storage devices such as flash memory devices are currently revolutionizing the data storage landscape. These devices are more rugged than conventional storage devices due to the absence of moving parts, and offer exceptional bandwidth, significant savings in power consumption, and random I/O (input/output) performance that is orders of magnitude better than hard disk drives (HDDs).
In some types of solid-state memory, the fundamental storage unit (the “cell”) can be set to only two levels and so can record only binary values. Other types of solid-state memory have so-called “multi-level cells” which can be set to q different levels, where q>2. For example, flash memory and phase change memory (PCM), two important non-volatile memory technologies, permit such multi-level recording. NOR flash memories, for instance, can store 4 levels, i.e. 2 bits, per cell. Multi-level cell (MLC) NAND flash memory chips that can store 4 bits of data per single flash cell using 43 nm process technology are currently available. The PCM technology is expected to supplant flash memory technologies when process technologies below 10 nm are required. Although commercially available PCM chips currently store only one bit per cell, storage of 4 bits per cell in PCM chips has already been experimentally demonstrated.
A challenge in multi-level SSSDs is drift noise. In particular, solid-state memory technologies such as flash and PCM suffer from a phenomenon known as “short-term drift,” or simply “drift.” In PCM, drift manifests itself as a monotonous increase of the resistance of the stored cell level with time. It is associated with the amorphous phase and is believed to be caused by short-range ordering of defects in the volume of the amorphous part of the cell. Drill of the amorphous or partially amorphous phases can be quite severe in PCM cells. Drift is a particular challenge for multi-level storage in memory cells as it may compromise reliability. Specifically, read-back values of neighboring levels may interfere over time, due to upward drift of the lower level towards the upper one, causing a detection error. The closer the initial spacing between levels the more susceptible they are to drift, so packing higher numbers of levels per cell becomes more difficult and the resulting memory is more prone to errors during cell state detection. On the other hand, packing more bits per memory cell is a key objective for all memory technologies as it is the best known method of reducing manufacturing cost per bit.
There have been a few proposals to tackle the problem of drift, though most remain at the academic interest level. One proposal is to use a certain part of the memory cell array as a reference pool of cells. These cells are written with known signal levels, and are continuously monitored during device operation, to obtain estimates of drift. The estimated drift values can then be used to update the level detection thresholds used to detect stored levels when reading the memory cell array.
Model-based drift cancellation techniques seek to model drift based on key parameters such as temperature, time and wear, and compensate accordingly. It is, however, difficult to obtain an accurate cell history for the key parameters. There are also fluctuations from cell to cell and there is no well-established analytical model available for short-term drift. A model-based approach using time-aware sensing is described in “Using Time-Aware Memory Sensing to Address Resistance Drift Issue in Multi-Level Phase Change Memory,” Wei Xu at al., Proc. Int'l Symposium on Quality Electronic Design, 2010. The proposed system keeps track of elapsed time between writing and reading of memory cells and uses this to estimate, and compensate for, the impact of time-dependent drift.
Drift acceleration is another proposal. The idea here is to thermally anneal the cell during programming so that drift, which is thermally activated, can saturate in a short period of time at elevated temperature.
Techniques based on coding have been proposed to address other problems in multi-level memories. For example, “Codes for Asymmetric Limited-Magnitude Errors with Application to Multi-Level Flash Memories,” Cassuto et al., Proc. International Symposium on Information Theory, 2007, discusses block codes designed to counter asymmetric noise-induced level shifts in some subset of a group of memory cells. Rank modulation has also been proposed to address endurance problems and overshoot errors in flash memories. This scheme is described in: “Rank Modulation for Flash Memories,” Jiang et al., IEEE Trans. Inf. Theory, vol. 55, no. 6, June 2009; and US Patent Application Publications Nos. 2009/0132895A1 and 2009/0132758A1. Rank modulation is also discussed in “Correcting Charge-Constrained Errors in the Rank-Modulation Scheme,” Jiang et al., IEEE Trans. Inf. Theory, vol. 56, no. 5, May 2010. As the name suggests, the fundamental principle of rank modulation is to store information in the rank order of a group of memory cells. In particular, stored information is represented by the rank order of a group of n multi level cells, named 1, 2, . . . n, each of which stores a different one of n levels, where cell rank is determined by the stored level in order from highest to lowest. Hence, the cell names 1, 2, . . . n, ordered according to rank, represent symbols of a stored codeword, with the n levels of the cells being used only to determine rank. In this way, the group of n cells can collectively form a virtual q-level cell, with levels 1 to q being defined by different codeword values in the n-cell group.